3D-ON-CHIP

3D Printing of Interconnections for Microelectronics
Aeronautics / Space/ Electronics / Additive Manufacturing
The 3D-on-Chip project aimed to demonstrate the feasibility of 3D-printed interconnections for microelectronics applications.
Selected under the RAPID program by the French Defence Innovation Agency (AID), the project focused on exploring new direct-write technologies to assess the viability of digital approaches to interconnection fabrication. Several direct printing technologies were leveraged to develop a new technological building block that could be integrated into the manufacturing of electronic components, while also demonstrating the reliability of the solution in terms of both thermomechanical behavior and the electrical performance of the metallic deposits.
To achieve this, various metallic and polymer inks were first formulated and then implemented using aerosol jet printing and micro-dispensing technologies. Once the microstructure of the printed traces was consolidated, their properties were assessed and demonstrators were tested.
The project partners were the CTTC (coordinator), and SERMA Microelectronics and Thalès Alenia Space.

Funded by the Direction Générale de l’Armement \ Agence de l’Innovation de Défense

Project carried out from 2019 to 2022
Budget : 1 000 000 €
Collaboration : CTTC, SERMA MICROELECTRONICS, THALES ALENIA SPACE
Results
The 3D-On-Chip project contributed to advancing our state of the art in direct-write technologies (Aerosol Jet Printing, Optomec) and filament-based deposition (microdispensing, nScrypt). The acquisition of a nScrypt printer marked a significant milestone in the CTTC’s roadmap by integrating a microdispensing process.
Combining this technology with Aerosol Jet Printing enabled the successful overcoming of technical barriers, such as demonstrating a functional interconnection solution between the substrate and surface-mounted microelectronic components. A dielectric material first had to be deposited to form bridging structures between different height levels, followed by the deposition of conductive tracks on top, thus enabling the connection of chip pads to substrate pads.